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  ProductsSOPC experimental platform seriesSOPC development platform for embedded multimedia experiments  
       SOPC development platform for embedded multimedia experiments  

Product name:SOPC development platform for embedded multimedia experiments

Products Category:SOPC experimental platform series

     

     Traditional CPLD / FPGA compared to laboratory equipment, the device can provide complete system design required for the experiment and interface various peripheral devices, including the most practical, the best test of peripheral devices such as audio, large LCD, the network interfaces. Through the core board can support 32-bit soft core processor, ALTERA's Nios II soft-core processor ALTERA the QuartusII software, you can in a very short period of time NIOS build a high-speed CPU, and can be customized IP core as well as custom user instructions, and can quickly complete UC Linux kernel to meet the teaching, curriculum design and graduate design project.

I、SOPC core board
      (1) CYCLONE NIOS-II EP2C35F48C8 chip
      (2) EEPROM chip, EPCS4
      (3) SRAM: 521K x 16bit Capacity
      (4) SDRAM: 4M × 32Bit SDRAM, 133MHz access speed.
      (5) FLASH: 16M byte

II、The basis of pilot projects
      (1) 4X4 Dot Matrix Keyboard test program
      (2) LCD16x2 LCD test program
      (3) 128x64 LCD test program
      (4) VGA display with 800x600 resolution display on the output side Bofan cases

            and sample letters.
      (5) 7-segment display control experiments
      (6) EEPROM: 93C46 read and write control experiments
      (7) I2C: 24LC02 read and write control experiments
      (8) PS / 2 interface and RS-232 interface for data transfer

      The basis of a total of more than 20 experiments and provide the source code.

III、NIOS part of the experiment
      (1) FPGA NIOS development to construct a complete platform and to LCD
    
           DEMO example, can be implemented within the program downloaded to 
  
           the FLASH experiment action
      (2) FPGA NIOS development to construct a complete platform and PC RS232
  
           communication experiment
      (3) FPGA NIOS development to construct a complete platform for testing 
           SRAM memory test
      (4) FPGA NIOS development of a complete platform for building and seven-
           segment LED display experiments
      (5) FPGA NIOS development to construct a complete platform for
    
           experimental testing program to read and write FLASH
      (6) FPGA NIOS development to construct a complete platform for audio
           experiments
      (7) FPGA NIOS development of a complete platform for building integrated 
           100MHz TCP / IP network communication experiment
      (8) FPGA developer to construct a complete platform for NIOS, NIOS system
           inspection program all experiments
      (9) FPGA NIOS development to construct a complete platform for the project
           after the experimental integrated Uc Linux OS
           Compiled and source code available.

 

     
     
   
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